In manufacturing a semiconductor device, photolithography is used as a patterning technology for forming a circuit pattern on a semiconductor wafer (hereinafter, referred to as a wafer) that is a substrate to be processed. To form a circuit pattern, photolithography is used by applying a resist liquid on a wafer to form a resist film, irradiating a light, exposing the resist film so as to correspond to the circuit pattern, and developing the exposed resist film.
Recently, semiconductor devices have a high integration tendency in view of improving operation speed. As such, miniaturization of a circuit pattern to be formed on a wafer is required in a patterning technology using photolithography. For this purpose, processes to shorten a wavelength of light, which is used in an exposing process, have been developed, but these processes do not fully satisfy the requirements for an ultrafine semiconductor device lower than the 45 nm node.
Therefore, as patterning technologies capable of satisfying the requirements of the ultrafine semiconductor device lower than the 45 nm node, upon forming a pattern of one layer, technologies for performing a number of patterning processes through photolithography have been proposed (for example, See Japanese Laid-Open Patent Publication No. (Hei) 7-147219). Among those, a technology for performing a patterning process twice is referred to as double patterning.
Also, as one technology of double patterning, there is a lithography-lithography etching (LLE). In LLE, a first-time patterning process is performed to form a first-time resist pattern and a second-time patterning process is performed to form a second-time resist pattern, such that an etching process is performed by using the first-time and second-time resist patterns as masks.
However, when a pattern resist is formed through double patterning technology using the above mentioned LLE, there are problems as follows.
In a typical single patterning of performing a patterning process one time, it is required to control or compensate a treatment condition in the patterning process in order to reduce a variation between wafers or in surfaces of the wafers, each of which has a line width (e.g., CD: Critical Dimension) of a resist pattern that is formed through the patterning process.
On the other hand, in double patterning using LLE, a first-time patterning process is performed to form a first-time resist pattern (e.g., a first resist pattern) and then a second-time patterning process is performed to form a second-time resist pattern (e.g., a second resist pattern). A treatment condition in the first-time patterning process is required to be controlled or compensated so as to reduce a variation between wafers or in surfaces of the wafers, each of which has a line width (e.g., CD) of the first resist pattern. Also, a treatment condition in the second-time patterning process is required to be controlled or compensated so as to reduce a variation between the wafers or in the surfaces of the wafers, each of which has a line width (e.g., CD) of the second resist pattern.
However, for example, when the afore-mentioned ultrafine patterning lower than the 45 nm node is performed, it may be difficult to reduce a variation between wafers or in surfaces of the wafers, each of which has a line width (e.g., CD) of the first resist pattern only by controlling or compensating a treatment condition in a first-time patterning process. Also, it may be difficult to reduce a variation between the wafers or in the surfaces of the wafers, each of which has a line width (e.g., CD) of the second resist pattern only by controlling or compensating a treatment condition in the second-time patterning process.